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Features
* * * * * * * * * * *
Organized as 2M x 8 bits Single 3.3V Power Supply Stacks of 16 SRAM 128K x AT65609E Die Access Time: 40 ns read, 35 ns write Very Low Power Consumption - Active: 130 mW (Typ) - Standby: 1 mW (Typ) TTL-Compatible Inputs and Outputs Die Designed on 0.35 Micron Process No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of 200 krads (Si) according to MIL STD 883 Method 1019 Wide Temperature Range -55C to +125C Built by 3D+ company, using 3D+ Die Stacking Technology and Tested by Atmel
Description
The AT61162E is a Rad Hard module, highly-integrated and very low-power CMOS static RAM organized as 2M x 8 bits. It is organized with 16 banks of 1 Mbit. Each bank has a 8-bit interface and is selected with 16 specific CS: 0 - 15. Banks are selectable by pairs with 8 specific BS: 0 - 7. This module takes full benefit of the 3D+ cube technology, and it is assembled by 3D+ and tested by Atmel, using Atmel 65609E 1-Mbit SRAM die: it is built with 8 layers, each one housing 2 dies. 10 nF decoupling capacitors are embedded for each memory die. This module brings the solution to applications where fast computing is as mandatory as low power consumption, for example: space electronics, portable instruments, or embarked systems. AT61162E is processed according to the methods of the latest revision of the MIL PRF 38535, QML N (QML Q counterpart for plastic). The package is a 64 gull wing pins dual in line, 11 mm wide, 28 mm long and 14.3 mm height and 0.8 mm pin pitch.
Rad Hard 2-Mbit x 8 SRAM Cube AT61162E
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Block Diagram
CS0.0 CS0.1 BS0 CS1.0 CS1.1 BS1 CS7.0 CS7.1 BS7
Bank 0 I/O (0:7) A (0:16) WE OE I/O (0:7) A (0:16) WE OE I/O (0:7) A (0:16) WE OE CS1 CS2 Chip 0 Chip 1 CS1 CS2
Bank 1 I/O (0:7) A (0:16) WE OE Chip 1 CS1 CS2
Bank 7 I/O (0:7) A (0:16) WE OE Chip 1 CS1 CS2
I/O (0:7) A (0:16) WE OE
CS1 CS2 Chip 0
I/O (0:7) A (0:16) WE OE
CS1 CS2 Chip 0
Pin Configuration
CS 7.0 CS 6.0 CS 5.0 CS 4.0 CS 3.0 CS 2.0 CS 1.0 CS 0.0 CS 0.1 CS 1.1 CS 2.1 CS 3.1 CS 4.1 CS 5.1 CS 6.1 CS 7.1
BS 7 BS 6 BS 5 BS 4 BS 3 BS 2 BS 1 BS 0
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Pin Description
Pin Name AO - A16 WE OE CS 0.0 - CS 7.1 BS0 - BS7 I/O0 - I/O7 Function Address Inputs Write Enable Output Enable Chip Select 1 Chip Select 2 Data Inputs/Outputs 3.3V Power Ground No Connection
VCC
GND NC
Truth Table
CSx.x All CS H BSx - WE - OE - Inputs/ Outputs Z Mode Deselect/ Power-down Deselect/ Power-down
- CS y.z: L Other CS: H CS y.z: L CS y.w: H Other CS: - CS y.z: L Other CS: H CS y.z: L CS y.w: H Other CS: - CS y.z: L Other CS: H CS y.z: L CS y.w: H Other CS: -
All BS L BSy: H Other BS: -
-
-
Z
H BSy: H Other BS: L BSy: H Other BS: - L BSy: H Other BS: L BSy: H Other BS: - H BSy: H Other BS: L
L
Data out
Read (Bank y.z selected)
-
Data in
Write (Bank y.z selected)
H
Z
Output Disable
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Electrical Characteristics
Absolute Maximum Ratings*
Supply Voltage to GND Potential............................ 0.5 to +5V DC Input Voltage GND ........................... GND -0.3 to VCC0.3V DC Output Voltage high-Z-State GND ... GND -0.3 to VCC+0.3V Storage Temperature ......................................... -65 to +150C Output Current into Outputs (Low)................................. 20 mA Electro Statics Discharge Voltage (MIL STD 883D method 3015.3).................................. >1000V
*Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Range
Operating Temperature Military -55C to 125C Operating Voltage 3.3V 0.3V
Recommended DC Operating Conditions
Parameter Description Supply Voltage Ground Input High Voltage Input Low Voltage Min 3 0 2.2 GND-0.3 Typ 3.3 0 0.0 Max 3.6 0 Units V V V V
VCC
Gnd V IH V IL
VCC+0.3
0.8
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DC Parameters
Parameter IIX
(1)
Description Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage
Min -10 -10 2.4
Typ -
Max 10 10 0.4 -
Unit A A V V
IOZ (1) VOL (2) VOH (3)
1. 2. 3.
Gnd < VIN < VCC, Gnd < VOUT < VCC Output Disabled. VCC min. IOL = 4 mA. VCC min. IOH = -2 mA.
Consumption
Symbol ICCSB ICCSB1 ICCOP
(1)
Description Standby Supply Current Standby Supply Current Dynamic Operating Current
61162E 24 16 60
Unit mA mA mA
Value max max max
(2)
(3)
1. 2. 3.
CS0.0 - CS7.1 > VIH or BS0 - BS7 < VIL and CS0.0 - CS7.1 < VIL. CS0.0 > VCC - 0.3V or, BS0 - BS7 < Gnd + 0.3V and CS0.0 - CS7.1 < 0.2V One bank active (F = 1/TAVAV, IOUT = 0 mA, W = OE = VIH, VIN = Gnd/VCC, VCC max.), other banks stand by TTL (note 1) or CMOS (note 2).
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Write Cycle
Symbol tAVAW tAVWL tAVWH tDVWH tE1LWH tE2HWH tWLQZ tWLWH tWHAX tWHDX tWHQX Parameter Write cycle time Address set-up time Address valid to end of write Data set-up time CS1 low to write end CS2 high to write end Write low to high-Z (1) Write pulse width Address hold from to end of write Data hold time Write high to low-Z (1) 61162E 35 0 25 20 30 30 10 30 +3 0 0 Unit ns ns ns ns ns ns ns ns ns ns ns Value min min min min min min max min min min min
Note:
1. Parameters guaranteed, not tested, with output loading 5 pF (see 1b in Figure: AC Test Loads Waveforms).
Read Cycle
Symbol tAVAV tAVQV tAVQX tE1LQV tE1LQX tE1HQZ tE2HQV tE2HQX tE2LQZ tGLQV tGLQX tGHQZ Parameter Read cycle time Address access time Address valid to low-Z Chip-select1 access time CS1 low to low-Z (1) CS1 high to high-Z (1) Chip-select2 access time CS2 high to low-Z (1) CS2 low to high-Z (1) Output Enable access time OE low to low-Z (1) OE high to high-Z (1) 61162E 40 40 3 40 3 15 40 3 15 15 0 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns Value min max min max min max max min max max min max
Note:
1. Parameters guaranteed, not tested, with output loading 5 pF (see 1b in page Figure: AC Test Loads Waveforms).
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AC Parameters
AC Test Conditions Input Pulse Levels: ....................................................... GND to 3.0V Input Timing Reference Levels: ................................... 1.5V Output Loading IOL/IOH (see figures 1a and 1b)............ +30 pF Rise and Fall times: Capacities, combined with current levels, impact on rise and fall times. The following table summarizes capacitance values (in pF), determined at 50.
WE / OE / Address Inputs 130 Data Inputs / Outputs 160
CSx.x
BSx
12
20
AC Test Loads Waveforms
R1 2552 3.3V R1 2552 3.3V
2824
2824
Figure 1a
Figure 1b
Figure 2
1340
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Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retention CS must be held high within VCC to VCC -0.2V or, chip select BS must be held down within GND to GND +0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power up and power down transitions CS and OE must be kept between VCC + 0.3V and 70% of VCC, or with BS between GND and GND -0.3V. 4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (3V).
Timing
3V
3V
BS
Data Retention Characteristics
Parameter VCCDR tCDR tR ICCDR1(2) Notes: Description VCC for data retention Chip deselect to data retention time Operation recovery time Data retention current at 2.0V 1. TAVAV = Read Cycle Time 2. All CS = VCC or All BS = CS = GND, VIN = Gnd/VCC. Min 2.0 0.0 tAVAV(1) - Typical TA = 25C - - - 0.040 Max - - - 12 Unit V ns ns mA
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Figure 1. Write Cycle 1. W Controlled, OE High During Write
Figure 2. Write Cycle 2. W Controlled, OE Low
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Figure 3. Write Cycle 3. CS1 or CS2 Controlled
Note:
The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and WE LOW. Both signals must be activated to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be referenced to the activated edge of the signal that terminates the write. Data out is high impedance if OE = VIH.
Figure 4. Read Cycle nb 1
Figure 5. Read Cycle nb 2
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Figure 6. Read Cycle nb 3
D
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Test Tools
Supplier ENPLAS Reference Number OTS - 64 - 0.8 - 04
Ordering Information
Reference Number AT61162E-PM40MMN AT61162E-PM40M-E Temperature Range -55 to +125C 25C Speed 40 ns 40 ns Package Cube 64 pins Cube 64 pins Quality Flow Atmel flow for plastic package (equivalent to MIL-PRF-38535 QML N) Engineering Samples
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Package Drawing
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